1. Field of the Invention
The present invention relates to an integrated circuit capable of high-speed and low-power operation and, more particularly, to a CMOS integrated circuit using U-grooved insulated gate static induction transistors achievable of a high-speed and low-power operation even when a supplied voltage is small.
2. Description of the Related Art
A CMOS integrated circuit using conventional MOS transistors is generally used in a random logic, a memory, or the like and its greatest feature is low-power operation. In this conventional CMOS integrated circuit, stored charges in a load capacitor C correspond to energy loss within a transient state (0.fwdarw.1, 1.fwdarw.0 or H.fwdarw.L, L.fwdarw.H). Power dissipation P can thus be expressed by the following equation. EQU P=C.times.V.sup.2 .times.f (V: Power supply voltage, f: Operation frequency)(1)
Since no current flows or no energy is dissipated in a steady state of the conventional CMOS integrated circuit, the circuit is characterized by low-power operation in view of its principle.
However, a conventional MOS transistor used for a CMOS integrated circuit is so designed as to use the vicinity of an interface between a semiconductor and an oxide film to move carriers. Therefore, the conventional MOS transistor has the drawback of poor drivability and low-speed operation.
The inventors of the present invention proposed a U-grooved insulated gate static induction transistor in, for example, Japanese Patent Application No. 52-1370, which eliminates the above drawback and has excellent characteristics as a high-speed switching device or a high-speed, low-power integrated circuits. Since this U-grooved insulated gate static induction transistor is so designed that the drain field effect reaches to the source, current flows in the substrate as well as in the interface between the semiconductor and insulation film. Therefore, the transistor has unsaturated current-voltage characteristics and high drivability. The transistor also has the advantage of decreasing a stray capacitance in view of its principle.
According to J. Nishizawa et al., "IEEE Transactions on Electron Devices," Vol. ED-37, No. 8, pp. 1877-1883 (1990), if a CMOS integrated circuit is formed using a U-grooved insulated gate static induction transistor on condition that a design rule is 1 .mu.m and the depth of a U-shaped groove is 0.5 .mu.m, the minimum switching time of 49 psec is obtained at a power dissipation of 7 mW.
In the CMOS integrated circuit of the U-grooved insulated gate static induction transistor, the power dissipation is determined by the same way as in the conventional CMOS integrated circuit, C.times.V.sup.2 .times.f, it is effective in low-power operation to decrease the supplied voltage.
However, the decrease in the supplied voltage also reduces the drivability of the U-grooved insulated gate static induction transistor and prevents a high-speed operation thereof. So, high speed operation is incompatible with low voltage operation even if the U-grooved insulated gate static induction transistor is used.